(Back to Sessions List)
Session 22 - Simulation and Modeling of Global Interconnect
Chairman: Ken Wagner - Siemens USA
Co-Chairman: Hidetoshi Onodera - Kyoto Univ.
8:30pm - Introduction
22.1 - 8:35pm
The Challenge of Designing Global Signals in UDSM CMOS, (tutorial)
S. Taylor, CMOS Solutions, Olga, WA
Abstract :
This paper describes several challenges facing designers of global
signals in high-performance UDSM CMOS designs. A practical
building-block approach is presented to solve or avoid problems with
global signals (including power) as technologies shrink to 0.25 micron
and below. Guidelines are presented for estimation, planning, and
implementation of global signals.
22.2 - 9:25am
Clock Verification in the Presence of IR-Drop in the Power Distribution
Network
S. Hussain, S. Rochel, D. Overhauser, R. Saleh, Simplex Solutions, Inc.,
Sunnyvale, CA
Abstract :
In this paper, we present a loosely coupled iterative technique for
clock verification in the presence of full-chip dynamic IR-drop. The
degradation in clock signal due to dynamic IR-drop is demonstrated with
small and large examples. We also discuss risks associated with assuming
a static IR-drop budget upon clock propagation.
22.3 - 9:50am
Characterization and Modeling of Clock Skew with Process Variations
P. Zarkesh-Ha, T. Mule, J. Meindl, Georgia Institute of Technology,
Atlanta, CA
Abstract :
A new compact model for on-chip clock skew as a function of device,
interconnect, and system parameter variations is derived. Unlike
previous models that describe qualitative behavior of clock skew
components, the new model provides a closed form expression for each
clock skew component. An example of clock skew components for a typical
design using 0.18um CMOS technology is investigated.
22.4 - 10:15am
Including Inductive Effects in Interconnect Timing Analysis
B. Krauter, S. Mahrotra, V. Chandramouli, IBM Corporation, Austin, TX
Abstract :
In this tutorial paper we describe the technology trends that made
inductance important in timing analysis, summarize when inductance
should be included, and consider some of the extraction and modeling
techniques available. We focus primarily on extraction methods that
efficiently capture frequency dependence due to proximity effects and
moment-based analysis techniques.
22.5 - 10:40am
Return-Limited Inductances: A Practical Approach to On-Chip
Inductance Extraction
K. Shepard, Z. Tian, Columbia University, New York, NY
Abstract :
This paper proposes a practical approach for extracting approximate
inductances of on-chip interconnect. This approach, which we call the
method of return-limited inductances, is based on performing the
inductance modeling of signal lines and power-ground lines independently
and on taking advantage of the power-ground distribution of the chip to
localize inductive coupling.
22.6 - 11:05am
An Efficient Inductance Modeling for On-chip Interconnects
L. He*, N. Chang, S. Lin, O. Nakagawa, Hewlett-Packard, Palo Alto, CA,
*University of California, Los Angeles, CA
Abstract :
In this paper, we present an efficient yet accurate inductance
extraction methodology. We first show that without loss of accuracy, the
extraction problem of n traces can be reduced to a number of one-trace
and two-trace subproblems. We then solve one-trace and two-trace
subproblems via a table-based approach. The table-based inductance model
has been integrated with a statistically-based RC model generation to
generate RLC models, with consideration of process variations, for
on-chip interconnects. Application examples show that our method is
efficient enough to be used during iterative procedures of interconnect
simulation and layout optimization.
22.7 - 11:30am
Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and
Characterization for Fast R, L Extraction
A. Sinha, University of California, Los Angeles, CA, S. Chowdhury,
Motorola, Austin, TX
Abstract :
For high-speed circuits, on-chip inductance can no longer be ignored.
This paper deals with inductance in the presence of muti-layered meshes
used for on-chip power supplies. We have shown ways of designing
power/ground (p/g) mesh that reduce inductance. Accurate 3-dimensional
inductance extraction problem is intractable for large chips. We have
demonstrated the feasibility of using flexible-accuracy empirical
formulae for fast determination of inductance. We have reported results
obtained from a real chip.
(Back to Sessions List)
Session 23 - Noise Issues in IC Design
Chairman: Mark Young - Filanet Corporation
Co-Chairman: Edoardo Charbon - Cadence Design
8:30pm - Introduction
23.1 - 8:35pm
Power Supply Noise in Future IC's: A Crystal Ball Reading (invited)
P. Larsson, Bell Laboratories, Lucent Technologies, Holmdel, NJ
Abstract :
di/dt noise is becoming more severe as technology scales, resulting in
great need for noise suppression techniques. Several techniques are in
use today, but only two techniques will remain effective in the future
as shown by scaling theory analysis. Resonance is a related issue that
will also be analyzed.
23.2 - 9:25am
Switching Well Noise Analysis and Minimization Strategy for Low Vth CMOS
Integrated Circuits
A. Koyama, M. Tsuge, J'Y. Kudo, T. Aida, M. Uchida, Hitachi Ltd., Tokyo,
Japan
Abstract :
An accurate equation and solution to estimate Switching Well Noise in
CMOS integrated circuits with low Vth is proposed. The propagation
characteristics of the noise are fully analyzed with a distributed
parameter model, which enables us to derive a novel design guideline and
layout strategy to minimize Switching Well Noise.
23.3 - 9:50am
Substrate Cross Talk Noise characterization and Prevention in 0.35um
CMOS Technology
J. Lee, F. Wang. A. Phanse, L. Smith, National Semiconductor, Santa
Clara, CA
Abstract :
The substrate cross talk noise characterization using s-parameter
measurement in 0.35um CMOS technology is presented. Frequency domain
analysis is used to study the layout geometry dependent noise mechanism.
Experimental approaches using guard ring, isolation bar, diffusion
width, physical separation, and dc bias technique are used to reduce the
substrate noise.
23.4 - 10:15am
Substrate Injection and Crosstalk in CMOS Circuits
J. Briaire*, **, K. Krisch*, *Bell Laboratories, Lucent Technologies,
Murray Hill, NJ, **Eindhoven University of Technology, Eindhoven, The
Netherlands
Abstract :
Substrate noise injection is evaluated for a 0.25um CMOS technology, to
determine the mechanisms that contribute to substrate crosstalk. Impact
ionization current and capacitive coupling are found to dominate
substrate current injection. Their relative importance in an inverter is
shown to depend upon loading and on the frequency of operation.
23.5 - 10:40am
A Methodology for Measurement and Characterization of Substrate Noise in
High Frequency Circuits
R. Garpurey, Texas Instruments, Inc., Dallas, TX
Abstract :
A method is proposed in this paper to measure and characterize substrate
noise in high-frequency circuits. Since substrate coupled signals are
small quantities, special precautions must be taken to isolate these
signals to avoid contamination by signals coupled through the package
and the board. The method proposed is based on sensing and
down-converting substrate signals on-chip to lower frequencies for
measurement. As an illustration of this general method we measure the
noise injected by an on-chip Voltage Controlled Oscillator (VCO) using
down-converting mixers as sensors.
23.6 - 11:05am
A Review of Substrate Coupling Issues and Modeling Strategies (invited)
R. Singh, Cadence Design Systems, San Jose, CA
(Back to Sessions List)
Session 24 - Analog Techniques
Chairman: Yusuf Haque - Maxim Integrated Products
Co-Chairman: Jose Cruz - Sun Microsystems
8:30pm - Introduction
24.1 - 8:35pm
A Wideband Tunable CMOS Channel-Select Filter for a Low-IF Wireless
Receiver
F. Behbahani, W. Tan, A. Karimi, A. Roithmeier, A. Abidi, University of
California, Los Angeles, CA
Abstract :
A variable BW, gm-c channel-select BPF is presented. The BW is variable
from 600 KHz to 10 MHz, while the lower edge frequency is kept at 5
MHz. It is implemented by cascading a 5th order elliptic filter and a
HPF. The HPF is implemented by using amplifiers with LPF in the feedback
loop. This filter has 50 nV/sq-Hz input referred noise and IIP3 of 22
dBm and 0 to 45 dB of gain, while draining 11 mA from a 3.3 V supply.
24.2 - 9:00am
A 1V 5th-Order Bessel Filter Dedicated to Digital Standard Processes
M. Python*, A-S. Porret*, C. Enz**, *Swiss Federal Institute of
Technology, Lausanne, Switzerland, **Rockwell Semiconductor System,
Newport Beach, CA
Abstract :
This paper presents the design of a 5th-order continuous-time Bessel
filter, which is realized using a CMOS transistors-only approach and a
pseudo-differential topology. The latter achieves a 57dB minimum dynamic
range even under 0.9V supply voltage. The power consumption is as low as
10.5uW at the nominal 100kHz cutoff frequency, while the total chip area
is only 0.2mm2.
24.3 - 9:25am
A 2Vpp Linear Input-Range Fully Balanced CMOS Transconductor and Its
Application to a 2.5V 2.5MHz Gm-C LPF
T. Itakura, T. Ueno, H. Tanimoto, T. Arai, Toshiba Corporation,
Kawasaki, Japan
Abstract :
A Fully balanced (FB) transconductor using two multi-input single-ended
CMOS transconductors is proposed. The FB transconductor achieves a 2Vpp
linear input range at 2.5V power supply and consumes 1.74mA. A 2.5MHz FB
Gm-C Filter using the transconductors achieves a CMRR of 45dB and a
passband IIP3 of 32dBm.
24.4 - 9:50am
A 2.125 Gbaud 1.6kOhm Transimpedance preamplifier in 0.5um CMOS
S. Mohan, T. Lee, Stanford University, Stanford, CA
Abstract :
A 2.125 Gbaud Fibre Channel compliant preamplifier employs a common-gate
input stage followed by a cascoded common-source stage with on-chip
inductive peaking to achieve a 1.6kOhm transimpedance and 0.6uA input
referred current noise, while operating with a photodiode capacitance of
0.6pF. A fully differential topology ensures good substrate and supply
noise immunity. The amplifier, implemented in a triple metal, single
poly, 14GHz fT(max), 0.5um CMOS process, dissipates 225mW of which 110mW
is consumed by the 50ohm output driver stage.
24.5 - 10:15am
A 5GHz, 1mW CMOS Voltage Controlled Differential Injection Locked
Frequency Divier
H. Rategh, H. Samavati, T. Lee, Stanford University, Stanford, CA
Abstract :
A voltage controlled differential injection locked frequency divider
(VCDILFD) with a large locking range is designed in a 0.24um CMOS
technology. A 29% locking range is achieved by an optimal inductor
design and also by employing high Q accumulation mode MOS varactors to
change the free-running oscillation frequency of the divider. The
measurement results show frequency division at 5GHz with more than 1GHz
locking range and power consumption of less than 1mW.
24.6 - 10:40am
A 3.25 GB/s Injection Locked CMOS Clock Recovery Cell
T. Gabara, Bell Laboratories, Lucent Technologies, Murray Hill, NJ
Abstract :
A clock signal embedded in a NRZ (Non Return to Zero) 2E31-1
pseudo-random data stream is used to injection lock a slave CMOS LC tank
circuit. A clock signal responsive to this stimulus is used to capture
the data. A measured Bit Error Rate (BER) of less than 2E-15 at 3Gb/s is
achieved using conventional 0.25um CMOS.
24.7 - 11:05am
A Novel High Precision Adjustment Method for the Transconductance of a
MOSFET
M. Tiilikainen, Nokia Research Center, Helsinki, Finland
(Back to Sessions List)
Session 25 - General Purpose and Application Specific Digital Signal Processing
Chairman: Alan Willson - University of California, Los Angeles
Co-Chairman: Neil Weste - Macquarie University
8:30pm - Introduction
25.1 - 8:35pm
A New Generation of DSP Architectures (invited)
B. Ackland, P. D'Arcy, Lucent Technologies, Holmdel, NJ
Abstract :
Today's general purpose DSPs provide moderate performance at very low
cost and low power. Circuit and architectural techniques for further
reducing power in portable applications are reviewed. New applications
will require very high performance at relatively low power with a much
improved programming model. Recent proposals for achieving these
somewhat conflicting goals are reviewed. A bus based multi-core
architecture for achieving greater parallelism is also described.
25.2 - 9:25am
A Single-Chip 1.6Billion 16-b MAC/s Multiprocessor DSP
B. Ackland, A. Anesko, D. Brinthaupt, S. Daubert, A. Kalavade, J.
Knobloch, E. Micca, M. Moturi, C. Nicol, J. O'Neill, J. Othmer, E.
Sackinger, K. Singh, J. Sweet, C. Terman*, J. Williams, Lucent
Technologies, Murray Hill, NJ, *MIT, Cambridge, MA
Abstract :
A MIMD multiprocessor DSP chip containing four 64-b processing elements
(PEs) interconnected by a 128-b pipelined split transaction bus (STBus)
is presented. Each PE contains a 32-b RISC core with DSP enhancements
and a 64-b SIMD vector co-processor with four 16-b MACS and a vector
reduction unit. PEs are connected to the STBus through re-configurable
dual-ported snooping L1 cache memories that support shared memory
multiprocessing using a modified-MESI data coherency protocol.
High-bandwidth data transfers between system memory and on-chip caches
are managed in a pipelined memory controller that supports multiple
outstanding transactions. An embedded RTOS dynamically schedules
multiple tasks onto the PEs. Process synchronization is achieved using
cached semaphores. The 120mm2 0.25um CMOS chip operates at 100MHz and
dissipates 4W from a 3.3V supply.
25.3 - 9:50am
A DSP Reed-Solomon Coder
T. Wolf, Texas Instruments Inc., Dallas, TX
Abstract :
Reed-Solomon (RS) codes are used in many of today's communications
systems. RS codes use finite field arithmetic which DPS's don't
implement efficiently. In previous RS hardware designs, a unique
hardware solution was designed for each system. In this paper we
describe a single hardware design which is programmable. This device
was designed to run in parallel with a DSP. The DSP would download the
RS function to the coder which would enable the DSP more MIPS for other
functions.
25.4 - 10:15am
Versatile Beamforming ASIC Architecture for Broadband Fixed Wireless
Access
J-N. Duan, L. Ko, B. Daneshrad, University of California, Los Angeles,
CA
Abstract :
This paper describes a highly flexible VLSI ASIC architecture targeted
for use in present and future broadband fixed wireless access
communication systems.The architecture features a novel structure for
variable rate interpolation that allows it to operate at any user
specified symbol rate from 625 kBaud to 10 MBaud. A unique shaping
filter structure with programmable CSD coefficients is also implemented.
The signal flow paths can also be reversed allowing the chip to be used
in both the transmitter and the receiver portions of a communication
system. Finally, anticipating operation in a TDMA network, all user
programmable features can be quickly changed for each time slot.
25.5 - 10:40am
A Single-Chip Narrowband Frequency Domain Excisor for a Global
Positioning System (GPS) Receiver
P. Capozza, B. Holland, T. Hopkinson, R. Landrau, The MITRE Corporation,
Bedford, MA
25.6 - 11:05am
470MHz Digital Filter on Delta-Sigma Modulated Signals
S. Li, D. Lewis, University of Toronto, Toronto, Ont., Canada
Abstract :
This paper describes a digital filter operating on modulated signals.
Using a simple processor core comprising an ALU and multiple registers,
controlled by an instruction ROM, this circuit operates at 470MHz in
0.8um CMOS. Novel features include partial carry propagation, which
reduces circuit delay to that of a single carry-save adder, but results
in inexact quantization. On-chip clocking synchronizes low-speed I/O
signals to the internal 470MHz clock. All-N TSPC and conventional TSPC
result in high clock speed of 470MHz in a 0.8um process.
Back to Sessions List