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Session 14 - Read/Write Channel Signal Processing
Chairman: L. Richard Carley - Carnegie Mellon University
Co-Chairman: Sang-Soo Lee - DataPath Systems
2:00pm - Introduction
14.1 - 2:05pm
Hard Disk Drive Read Channels: Technology and Trends (invited)
H. Thapar, S-S. Lee, C. Conroy, R. Contreras, A. Yeung, J-G. Chern, T.
Pan, S-M. Shih, DataPath Systems, Inc., Los Gatos, CA
Abstract :
This paper provides an overview of HDD read channel technology and
trends. Dominant channel impairments are discussed along with signal
processing methods to mitigate their effects. Equalization, coding
techniques, and circuit design challenges in meeting the emerging data
rate requirement of 1 Gb/s in read channel products are discussed.
14.2 - 2:55pm
A 450Mbit/s EPR4 PRML Read/Write Channel
M.Demicheli, G.Bollati, P.Gadducci, L.Affortunati, R.Alini, G.Betti,
I.Bietti, F.Brianti, M.Bruccoleri, M.Coltella, P.Demartini, S.Marchese,
D.Ottini, V.Pisati, S.Portaluri, A.Rossi, P.Savo, C.Tonci, R. Castello,
STMicroelectronics, Cornaredo, Milan, Italy, *Universita di Pavia,
Pavia, Italy
Abstract :
A fully-integrated PRML Read/Write IC with digital adaptive FIR
operating up to 450Mbit/s is presented. The chip implements an EPR4
Viterbi detector as well as a digital servo. The device is integrated in
a 0.35um technology, has a die size of 11.44mm2 and dissipates 1.3W at
450Mbit/s.
14.3 - 3:20pm
A CMOS Two-Path Tree Search Detector
X. Wang, R. Spencer, University of California, Davis, CA
Abstract :
Two-path tree search (TPTS) is a detection algorithm combining a
decision-feedback equalizer (DFE) and a two-path tree search estimator.
This sub-optimal tree search overcomes the exponential increase in
hardware complexity with the tree length in a fixed-delay tree search
(FDTS) structure. An adaptive mixed-signal CMOS TPTS detector is
presented in this paper. The IC occupies 2.77mm by 2.44mm (including the
bonding pads) in a 0.5um CMOS process. It performs about 0.8dB better
than a conventional DFE in a disk drive read channel.
14.4 - 3:45pm
A 110Mhz 350mW 0.6u CMOS 16-State Generalized-Target Viterbi Detector
for Disk Drive Read Channels
S. Sridharan, L. Carley, Carnegie Mellon University, Pittsburgh, PA
Abstract :
A 16-state generalized-target Viterbi detector for disk drive read
channels, offering 4-5X lower error rate then EPR4-ML detectors,
requires 9 mm2 of die area in 0.6um 3.3V CMOS process. Operating at
110Mhz and 3.0 Volts, the Viterbi detector consumes under 350mW.
14.5 - 4:10pm
A BiCMOS Preamplifier/Write-driver IC for Tape Drive
M. Flynn, M. Twohig, R. Byrne, H. Reyhani, J. Ryan, Silicon Systems
Limited, Cork, Ireland
Abstract :
A single-supply 5V preamplifier IC for magneto-resistive (MR) read
element tape drive incorporates six independent differential read
amplifiers, and four independent write drivers. MR bias current
direction steering is included without additional switches in the signal
path. With a 39 Ohm read element the measured input referred noise is
1.0nV/sqrt(Hz).
14.6 - 4:35pm
A BiCMOS 1X to 5X Combined Analog Frontend IC for DVD-ROM & Movie
Players
S. Marchese, V. Pisati, S. Portaluri, A. Savo, G. Vai,
STMicroelectronics, Milan, Italy, S. Lehr, V. Neiss, C. Buechler, F.
Zucker, Thomson Multimedia, Villingen, Germany
Abstract :
All analog functions for 1X to 5X DVD and 1X to 32X CD are integrated on
a single 0.7um BiCMOS chip. It supports multi-media operation including
DVD-RAM, DVD-ROM, DVD-R, DVD Movie, CD, CD-ROM, CD-R and CD-RW. The chip
occupies 30mm2 and dissipates 900mW at 5V and full power on.
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Session 15 - Advanced Technologies for SOC and RF ICs
Chairman: Paul Tsui - Motorola
Co-Chairman: Joop Bruines - Philips Semiconductor
2:00pm - Introduction
15.1 - 2:05pm
Device and Circuit Design Issues in SOI Technology (invited)
G. Shahidi, A. Ajmera, F. Assaderaghi, R. Bolam, H. Hovel, E.
Leobandung, W. Rausch, D. Sadana, D. Schepis, L. Wagner, L. Wissel, K.
Wu, B. Davari, IBM Semiconductor Research and Development Center,
Hopewell Junction, NY
Abstract :
Partially-depleted deep sub-micron CMOS on SOI technology is becoming a
mainstream technology. This technology offers 20-35% performance gain
over a bulk technology implemented with the same lithography. This
paper first reviews the partially-depleted SOI device and describes
reasons why it was chosen over fully depleted SOI device. Next the
sources of performance gain on SOI are reviewed. SOI-unique circuit and
technology issues that a designer must consider and account for are
discussed next. Finally, a low-power application of SOI is reviewed.
15.2 - 2:55pm
The First Copper ASICs: A 12M-Gate Technology
J. Panner, T. Bednar, P. Buffet, D. Kemerer, D. Stout, P. Zuchowski IBM
Microelectronics Division, Essex Junction, VT
Abstract :
This paper describes the first CMOS ASIC logic family built with copper
metallurgy. Chips with up to 12-million equivalent gates can be
designed in the 0.16um process. The technology, product
characteristics, CAD system and first customer chips are discussed.
15.3 - 3:20pm
Wireless Communication Integrated Circuits with CMOS-compatible SiGe HBT
Technology Modules, (tutorial)
W. Winkler, J. Borngraber, He. Erzgraber, Ha. Erzgraber, B. Heinemann,
D. Knoll, H. Osten, M. Pierschel, K. Pressel, P. Schley, Institute for
Semiconductor Physics, Frankfurt, Germany
Abstract :
Despite rapid progress in the field of RF CMOS, there is a growing
interest in SiGe bipolar technology for RF and high speed applications.
We have developed a 0.8um SiGe HBT technology with ft/fmax of 45/50 GHz
(standard version for prototyping foundry operations) and an advanced
SiGe:C technology with ft/fmax of 50/90 GHz (experimental status). These
technologies are low cost modules that allow integration into existing
CMOS technologies with less than five additional masks. Further, a low
parasitics module is introduced.
In the first part of this
paper, the technology of the modules is described. In the second part
the devices for the design of RF circuits are presented. The spectrum of
devices includes: bipolar transistors, polysilicon resistors, MIM
capacitances, inductors and varicaps. In the third part circuit results
are presented. They include ring oscillators, VCOs, an LNA and a divider
for RF applications in the GHz range.
15.4 - 4:10pm
Pre-Silicon Parameter Generation Methodology using BSIM3 for
Device/Circuit Concurrent Design
M. Miyama, S. Kamohara, M. Hiraki, K. Onozawa, H. Kunitomo*, Hitachi
Ltd., Tokyo, Japan, *Hitachi ULSI Systems Co., Ltd., Japan
Abstract :
We present a physical parameter extraction methodology for BSIM3 to
generate accurate pre-silicon parameters (parameters created before
device fabrication). Parameters of the 0.20um process device can be
generated from a 0.25um technology with 5% accuracy in a few minutes. We
applied this method in optimizing the devices of our microprocessor.
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Session 16 - Noise Modeling and Simulation In Communications Circuits
Chairman: David Rich - Lucent Bell Laboratories
Co-Chairman: Trudy Stetzler - Texas Instruments
2:00pm - Introduction
16.1 - 2:05pm
Substrate-Induced High-Frequency Noise in Deep Sub-Micron MOSFETs for RF
Applications
S. Kishore*, G. Chang*, G. Asmanis**, C. Hull*, F. Stubbe**,
*SiliconWave, San Diego, CA, **Rockwell, Newport Beach, CA
Abstract :
We present results from high-frequency noise measurements on NMOS
devices fabricated in a 0.5-um epi-based CMOS process. These noise
measurements at RF frequencies reveal the existence of substrate-induced
high-frequency noise in transistors operating in the saturation regime.
The substrate-induced noise is independent of the transistor bias
conditions, but is strongly dependent on the geometry of the device and
the MOS gate-to-bulk capacitance. A new ac noise model for CMOS devices
operating at RF frequencies presented here shows good conformity to
measurements. Its implications are emphasized via the design of a
low-noise amplifier (LNA) operating at 2 GHz. The minimum achievable
noise-figure (NF) can be higher by as much as 0.6 dB due to this
substrate-induced high-frequency noise.
16.2 - 2:30pm
RF Simulations and Physics of the Channel Noise Parameters within MOS
Transistors
T. Manku, M. Obrecht, Y. Lin, University of Waterloo, Waterloo, Ont.,
Canada
Abstract :
In this paper we report results for the RF channel noise parameters of
MOS transistors. The results were obtained from a physically based 2-D
device noise simulator. The drain channel noise as well as the induced
gate noise are presented.
16.3 - 2:55pm
Phase Noise in Oscillators: A Tutorial (invited)
T. Lee, Stanford University, Stanford, CA
Abstract :
Abstract: Surprisingly, oscillators may be treated as linear, but
time-varying systems. This tutorial will examine precisely how device
noise turns into phase noise. Limitations of older linear time-invariant
models (e.g., the Leeson model) will be identified, and ways to exploit
new implications of the time-varying model will be described.
Illustrative circuit examples in CMOS will be presented to underscore
key insights.
16.4 - 3:45pm
Noise Analysis of a VCO with Automatic Amplitude Control
M. Margarit*, **, J. Tham*, M. Deen**, R. Meyer***, *Rockwell
International, Newport Beach, CA, **Simon Fraser University, Vancouver,
BC, Canada, ***University of California, Berkeley, CA
Abstract :
The noise analysis of a VCO with automatic amplitude control presented
in this paper is intended to identify the most important noise sources
in the circuit. The goal of this analysis is to find the optimum
trade-off between noise performance and power consumption. The
implemented VCO operates in the 300MHz to 1.2GHz frequency range using
different external resonators. The measured phase noise level is
106dBc/Hz at 100kHz offset from a 800 MHz carrier and it consumes 1.6mA
from a 2.7V power supply.
16.5 - 4:10pm
Modeling and Simulation of Noise in Analog/Mixed-Signal Communication
Systems (invited)
A. Demir, J. Roychowdhury, Bell Laboratories, Murray Hill, NJ
Abstract :
Noise in analog and mixed-signal electronic systems is an undesired but
unavoidable excitation on the circuit. Its analysis and modeling is
relatively straightforward in linear analog circuits, such as
amplifiers. For such circuits, the SPICE AC noise analysis is, most of
the time, adequate for noise performance characterization. However, for
communication circuits, where nonlinearities and frequency translation
are inherent, SPICE AC noise analysis is not adequate. Recently, there
has been a great deal of activity, both in the design and CAD
communities, to develop noise analysis techniques and tools to treat
problems with nonlinear and frequency translation effects. In this
tutorial, we first present the basic concepts and fundamental techniques
used in noise analysis and modeling both for linear and nonlinear
circuits. Then, we concentrate on some specific noise modeling and
analysis problems in mixed-signal communication system design, e.g.,
mixers, phase noise and timing jitter, digital switching interference,
etc.
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Session 17 - IP Reuse and Infrastructure
Chairman: Iraj Masarati - Avanti
Co-Chairman: Jake Buurma - Cadence Design Systems
2:00pm - Introduction
17.1 - 2:05pm
IP Reuse Creation for System-on-a-Chip Design (invited)
P. Bricaud, Mentor Graphics, Sophia Antipolis, France, M. Keating,
Synopsys
Abstract :
The never ending increase of silicon capacity available to system and IC
designers, as predicted by Moore's Law, brings on a cyclical crisis in
design methodology and engineering productivity generating a ripple
effect through the EDA and electronics industries. The System-on-a-Chip
era will need more than available silicon to become a reality. A new
design methodology roadmap based on IP reuse needs to emerge. Two of
the EDA giants, Synopsys and Mentor Graphics, took the initiative at DAC
1997 to set the pace for the new challenge of System-on-a-Chip design.
After more than a year and the publishing of the Reuse Methodology
Manual (RMM) that sets the stage for IP Reuse and System-on-a-Chip
design, where do we stand? The Reuse Methodology Manual is well
perceived and accepted by the design community and represents a stake in
the ground towards ensuring rapid creation of reusable designs.
Throughout this tutorial an attempt is made to describe the total SoC
design flow based on reusable IP and will also outline some non-trivial
issues during this process: effect of available silicon capacity, SoC
integration, SoC verification and documentation.
17.2 - 2:55pm
OwL: An Interface Description Language for IP Reuse
K. Suzuki, K. Ara, K. Yano, Hitachi Ltd., Tokyo, Japan
Abstract :
A new language for the interface description, named OwL, and its
applications are proposed. The purpose of OwL is reuse of IPs. By
specifying the functionality of the IP as an interface protocol, the IP
can be used as a blackbox. The interface specification of an SDRAM,
including refresh control, can be represented with 205 lines of OwL
description.
17.3 - 3:20pm
A New Method for Reuse-Driven Design of Digital Circuits
O. Heuser, H-L. Fiedler, Fraunhofer-Institute of Microelectronic
Circuits and Systems, Duisburg, Germany
Abstract :
The paper describes a method for the design of digital systems that
emphasizes a bottom-up procedure and reuse of existing components. Our
method is based on an object-oriented hierarchy of classes describing
the structure of components. Descriptions of all classes in the new
language HDLC++ are transformed into RTL-Verilog code for the complete
system.
17.4 - 3:45pm
An Integrated Environment for Configurable Designs
D. Dignam, B. Garlick, E. Hutchins, O. Rubinstein, GigaPixel
Corporation, Santa Clara, CA
Abstract :
Challenges arise in delivering IP content to meet the requirements of a
range of IP consumers. We describe an overall design methodology which
allows IP features and performance to be customized and rapidly deployed
to new libraries. These techniques are also appropriate outside of the
IP model when design reuse and robustness are critical.
17.5 - 4:10pm
IP Repository, A Web based IP Reuse Infrastructure
P. Schindler, K. Weidenbacher, T. Zimmermann, Motorola GmbH, Munich,
Germany
Abstract :
To hit the ever shorter market window for System on Chip (SoC) designs
it is essential to reuse existing design components also often described
as Intellectual Property (IP). Easy search, select and efficient
integration of available IP in a global, multi-site development
environment is a key enabler for fast SoC development. In this paper, we
present a Web enabled IP Reuse Infrastructure for IP consumers and
providers, delivering search, select, upload and download capabilities.
A central place for one stop IP shopping - the IP Repository.
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