(Back to Sessions List)
Session 10 - Wireless Transceivers and Systems
Chairman: Georges Gielen - Katholieke Universiteit, Leuven
Co-Chairman: Trudy Stetzler - Texas Instruments
8:30pm - Introduction
10.1 - 8:35pm
RF Transmitter Architectures and Circuits (invited)
B. Razavi, University of California, Los Angeles, CA
10.2 - 9:25am
A 4-dB NF GPS Receiver Front-end with AGC and 2-b A/D
M. Cloutier, T. Varelas, C. Cojocaru, F. Balteanu, Philsar Electronics,
Inc., Ottawa, Ont., Canada
Abstract :
A GPS receiver front-end downconverts and digitizes the GPS-L1 signal. The
chip includes LNA, 38dB IR-mixer, VCO-PLL, 55dB AGC, 2-b A/D and crystal
oscillator. The 4dB noise figure receiver uses a 3V/49mA supply. The AGC
and A/D offer better SNR and blocking performance than the commonly used
1-b quantizers.
10.3 - 9:50am
Mixed-Signal Quadrature Demodulator with a Multi-Carrier Regeneration
Systems
J. van Lammeren, Philips Semiconductors, Nijmegen, The Netherlands, R.
Wissing, Philips Research Laboratories, Eindhoven, The Netherlands
Abstract :
This paper presents a combined analogue/digital demodulation system that
features digital carrier regeneration controlled by a sigma-delta
converter with a combined decimation/loopfilter which acts on the
analogue signal path via two four-quadrant multiplying DACs to retrieve
the I and Q signals.
10.4 - 10:15am
An Ultralow Power Single-Chip 900 MHz CMOS Receiver for Wireless Paging
H. Darabi, A. Abidi, University of California, Los Angeles, CA
Abstract :
A CMOS dual-conversion zero-IF receiver tuned to 930 MHz dissipates 4.5
mW from a 1.5 V supply. The whole receiver including the on-chip channel
selection low-pass filter achieves a cascade noise figure of 7.4 dB and
an IIP3 of -25 dBm, using a VCO with -98 dBc/Hz open-loop phase noise at
a 25 kHz offset.
10.5 - 10:40am
A 5.2 GHz 3.3V I/Q SiGe RF Transceiver
J-O. Plouchart, H. Ainspan, M. Soyuer, IBM T.J. Watson Research Center,
Yorktown Heights, NY
Abstract :
A 5.2 GHz I/Q RF transceiver using a 0.5-um SiGe BiCMOS technology is
designed and measured. The receiver exhibits a 11.7 dB down-conversion
gain, a DSB noise figure of 7.5 dB, an input IP3 of -11.2 dBm, and an
amplitude imbalance of 0.33 dB for a 300 MHz IF. For the transmitter an
up-conversion gain of 14.7 dB, an output 1-dB compression point of -23
dBm, an amplitude imbalance of 0.5 dB, and a 7 GHz 3 dB bandwidth were
measured. The power consumption is 122mW for the receiver and 114 mW for
the transmitter at 3.3V power supply.
10.6 - 11:05am
A Si/SiGe HBT Timing Generator IC for High-Bandwidth Impulse Radio
Applications
D. Rowe, B. Pollack, J. Pulver, W. Chon, P. Jett*, L. Fullerton*, L.
Larson**, Sierra Monolithics, Redondo Beach, CA, *Time Domain Systems,
Inc., Huntsville, AL, **University of California, San Diego, CA
Abstract :
A precise timing generator is presented, which forms the heart of a
wideband impulse radio or radar system. The circuit is implemented in a
45 GHz Si/SiGe HBT technology, and can produce a pulse inside a 100 ns
window with an accuracy of 2 ps and a jitter of less than 10 ps. The
integrated circuit contains a mixture of analog, digital, and RF
functions, consumes 0.5 W, and operates at a clock rate of up to 2.5
GHz.
(Back to Sessions List)
Session 11 - Embedded Memory Circuits and Techniques
Chairman: Larry Wissel - IBM Microelectronics
Co-Chairman: Ranbir Singh - Lucent Microelectronics
8:30pm - Introduction
11.1 - 8:35pm
Converting a SRAM From Bulk Si to Partially Depleted SOI
M. Wood, G. Smith, J. Pennings, IBM Mid Hudson Valley High Performance
Design Center, Poughkeepsie, NY
Abstract :
The conversion of an existing standard cell compatible SRAM macro to a
partially depleted SOI process is described. The issues discovered in
the conversion were: changed coupling capacitance and noise analysis,
history effects in the sense amplifier, setup and hold time analysis and
thermal effects. For each of these effects the steps taken to meet
functionality requirements are explained.
11.2 - 9:00am
Multiple Twisted Data Line Techniques for Coupling Noise Reduction in
Embedded DRAMs
D-S. Min and D. Langer, University of Pittsburgh, Pittsburgh, PA
Abstract :
New multiple twisted data line techniques to reduce both bit line (BL)
and word line (WL) coupling noises in scaled embedded DRAMs are proposed
and analyzed. An improved noise/signal ratio resulting from the
application of the proposed techniques is confirmed by soft-error rate
measurements on test chips with 256-Mbit and 1-Gbit level integration.
At the 256-Mbit level, when the proposed techniques are applied to both
the BL and WL structures, we achieved a 64% coupling noise reduction
compared to the conventional twisted BL (TBL) and WL schemes.
11.3 - 9:25am
A 1.8V, 2.0ns Cycle, 32KB Embedded Memory with Interleaved
Castout/Reload
S. Sullivan, B. Johnson, D. Reid, S. Taylor, Motorola Somerset Design
Center, Austin, TX
Abstract :
This paper describes the key circuit features of the 32KB data cache
memory embedded in the first AltiVec(TM) enhanced PowerPC(TM)
microprocessor. The design incorporates self-resetting and dynamic
circuit techniques to achieve a cycle time of less than 2.0ns fabricated
in a 1.8-volt, 0.2um, 6-layer copper CMOS process.
11.4 - 9:50am
A Self-Timed, Fully-Parallel Content Addressable Queue for Switching
Applications
J. Podaima, G. Gulak, University of Toronto, Toronto, Ont., Canada
Abstract :
A self timed, fully parallel content addressable queue (CAQ) memory
replaces traditional means of implementing "pointer based" queuing in
switching systems. A 16.5 Kb "CAQ" test device implemented in 0.8um CMOS
asynchronously performs four memory operations per clock cycle. Test
results indicate a maximum operating frequency of 40 MHz.
11.5 - 10:15am
A 1.4V 60MHz Access, 0.25um Embedded Flash EEPROM
T. Kataoka, I. Fuchigami, Y. Nishida, T. Kimura, R. Aruga*, Y. Okuda**,
J. Michiyama, Matsushita Electric Industrial Co., Ltd., Fukuoka,
*Kawasaki, **Matsushita Electronics Corporation, Kyoto, Japan
Abstract :
We have developed a low voltage, high speed access (60MHz @ 1.4V, 145MHz
@ 2.5V), embedded Flash EEPROM. A new booster circuit has supplied a
stable voltage to the word-line, and a current comparing sense amplifier
has reduced an access time in the wide voltage range. An interleave
architecture has doubled operating frequency.
11.6 - 10:40am
Analog Sense Amplifiers for High Density NOR Flash Memories
M. Pasotti, P. Rolandi, R. Canegallo, D. Gerna, G. Guaitini, F. Lhermet,
A. Kramer, STMicroelectronics, Agrate, Italy
Abstract :
Three different types of analog sense amplifiers (ASA) are presented
that offer the precision needed for the storage of up to 6bit/cell in
standard NOR Flash memories for embedded mass storage applications.
Three test chips with 1Mcells array have been integrated in a 3V 0.5um
common-ground double metal double poly standard NOR flash-EEPROM
technology for embedded memory to validate the circuits.
(Back to Sessions List)
Session 12 - LAN/WAN Transceiver Technology
Chairman: Jerry Molnar - Mitel Semiconductor
Co-Chairman: Nick Van Bavel - Cicada Semiconductor
8:30pm - Introduction
12.1 - 8:35pm
A CMOS Mixed-Signal 100Mb/s Receive Architecture for Fast Ethernet
A. Shoval, O. Shoaei, K. Lee, R. Leonowich, Lucent Technologies,
Allentown, PA
Abstract :
A 125Mbaud quad transceiver for 10/100 fast ethernet has been designed
in a 5V 0.35um digital CMOS process. Power consumption for the device is
3W. Detailed testing shows excellent receiver results with error free
performance up to 160m under worst-case baseline wander and crosstalk
conditions. The analog receiver uses digital adaptation circuitry to
optimize an automatic gain control circuit with baseline wander
correction, an equalizer and a DC offset correction circuit.
12.2 - 9:00am
A Dual-Speed 125Mbaud/10Mbaud CMOS Transmitter for Fast Ethernet
O. Shoaei, A. Shoval, R. Leonowich, Lucent Technologies, Allentown, PA
Abstract :
A 10Mbaud waveshaping and current-mode line driver for 10Base-T and a
125Mbaud current-mode line driver for 100Base-TX/FX dual-speed
transmitter for a Fast Ethernet transceiver chip are presented. Their
power consumption from a single 5V supply are 200mW and 125mW
respectively. Transmitter die area for both is 0.764mm2 in a 0.35um
digital CMOS process.
12.3 - 9:25am
Clock and Data Recovery for 1.25 Gb/s Ethernet Transceiver in 0.35um
CMOS
K. Iravani, F. Saleh*, D. Lee, P. Fung, P. Ta, G. Miller*, VLSI
Technology, Inc., San Jose, CA, *Independent Consultant, San Jose, CA
Abstract :
A Clock/Data Recovery (CDR) PLL with VCO running at half the rate for
gigabit serial data communications is described. A novel feedback
biasing circuit technique is used between the VCO and the Charge-Pump to
minimize any systematic phase offset error due to process and
temperature variations. The receiver gain is boosted at high
frequencies to compensate for the loss introduced by the cable.
Improved CML logic is used to broadband the signal path. The core
consumes 150mW at 3.3V in 0.35um CMOS, and has the Bit-Error Rate (BER)
of 10E-14 for the input jitter of 500ps.
12.4 - 9:50am
A 1.25GHz 0.35um Monolithic CMOS PLL Clock Generator for Data
Communications
L. Sun, T. Kwasniewski, Carleton University, Ottawa, Ont., Canada
Abstract :
A 1.25GHz monolithic CMOS PLL clock synthesis unit was designed for data
communications. The monolithic PLL consists of a ring oscillator,
divider, phase/frequency detector, charge pump and an on-chip loop
filter. The voltage controlled oscillator incorporates a quadrature
output ring structure with sub-feedback loop embedded to speed up the
circuit. The PLL has been fabricated in a 0.35um CMOS process, occupies
an active area of 1mm2 and consumes 100 mW of power at 3.3V.
12.5 - 10:15am
A 3V-CMOS Low Distortion Class AB Line Driver Suitable for HDSL
Applications
M. Kappes, Conexant Systems Inc., San Diego, CA
Abstract :
A fully integrated CMOS line driver for use in High Bit-Rate Digital
Subscriber Line (HDSL) services is presented. The circuit features
<-70 dB THD when driving up to +/- 2.4V, 200 kHz signals into 30 ohms
while dissipating less than 60mW of quiescent power with a 3V supply.
12.6 - 10:40am
A 2.5-GB/s One-Chip Receiver Module for Gigabit-To-The Home (GTTH)
System
M. Soda, S. Shiori, T. Morikawa, M. Tachigori, I. Watanabe, M.
Shibutani, NEC Corporation, Kanagawa, Japan
Abstract :
A 2.5-Gb/s optical receiver module using a one-chip receiver IC has been
developed for an ultra-broadband optical access system. The IC fully
includes 3-R function required for optical receiver. The IC is packaged
in a compact ceramic package with an APD by passive alignment
technology. The module size is 14x19mm2 with a power consumption of the
450 mW at +3.3 V supply voltage.
(Back to Sessions List)
Session 13 - Custom Circuit Techniques for High-Performance and Low-Power
Applications
Chairman: Takayasu Sakurai - University of Tokyo
Co-Chairman: Larry Starr - Visteon Microelectronics
8:30pm - Introduction
13.1 - 8:35pm
Design Considerations for Distributed Microsensor Systems (invited)
A. Chandrakasan, R. Amirtharajah, S-H. Cho, J. Goodman, G. Konduri, J.
Kulik, W. Rabiner, A. Wang, Massachusetts Institute of Technology,
Cambridge, MA
Abstract :
Wireless distributed microsensor systems will enable the reliable
monitoring and control of a variety of applications that range from
medical and home security to machine diagnosis, chemical/biological
detection and other military applications. The sensors have to be
designed in a highly integrated fashion, optimizing across all levels of
system abstraction, with the goal of minimizing energy dissipation. This
paper addresses some of the key design considerations for future
microsensor systems including the network protocols required for
collaborative sensing and information distribution, system partitioning
considering computation and communication costs, low energy electronics,
power system design and energy harvesting techniques.
13.2 - 9:25am
A Single Chip CMOS APS Camera with Direct Frame Difference Output
S-Y. Ma, L-G. Chen, National Taiwan University, Taipei, Taiwan
Abstract :
A CMOS active pixel sensor with direct frame difference output is
reported in this paper. The proposed pixel circuit includes a
photodiode and 9 transistors and is optimized for low voltage operation.
A 128x96 pixel prototype camera chip with an on-chip 8-bit pipeline ADC
was fabricated in a 0.5um double poly double metal CMOS process. At
3.3V, the power dissipation is 56mW.
13.3 - 9:50am
Band Runlength Coding for Low-Power Continuous Micro Monitors
M. Fujishima, Y. Kiniwa, K. Hoh, The University of Tokyo, Tokyo, Japan
Abstract :
A novel data compression algorithm for low-power continuous
micro-monitoring systems is proposed. The algorithm is based on
runlength data coding dedicated to multi-bit signals generated by an A/D
converter and named Band Runlength (BRL) coding.
13.4 - 10:15am
A Data-driven Micropipeline Structure using DSDCVSL
S. Mathew, R. Sridhar, The State University of New York, Buffalo, NY
Abstract :
Micropipelines have been used in self-timed systems to increase the
throughput of the data path. However, the potential speedup is limited
by the overhead due to handshaking between adjacent stages. Data-driven
Differential Cascode Voltage Switch Logic (DSDCVSL) can be used to
design efficient self-timed pipeline structures, wherein the handshaking
overhead is minimized, due to implicit completion signal generation.
This paper defines a new data-driven micropipelined structure that shows
a 30% improvement in throughput and latency over existing systems.
13.5 - 10:40am
A 62.5 - 250 MHz Multi-Phase Delay-Locked Loop Using a Replica Delay
Line with Triply Controlled Delay Cells
Y. Moon, J. Choi, K. Lee, D-K Jeong, M-K. Kim*, Seoul National
University, Seoul Korea, *Silicon Image Inc., Cupertino, CA
Abstract :
This paper describes a low-jitter multi-phase delay-locked loop (DLL)
with a wide operating range of 62.5-250 MHz. A replica delay line
attached to the core DLL enables it to fully utilize the frequency range
of its voltage-controlled delay line. The DLL incorporates dynamic phase
detectors and triply controlled delay cells with duty-cycle correction
capability to generate equally spaced eight-phase clocks. The chip is
fabricated using a 0.35um CMOS process. The measured jitter is
suppressed to be less than 44 ps peak-to-peak over the operating
frequency range in a noisy environment with other digital circuits
activated on the same chip.
13.6 - 11:05am
A +/-25ps Jitter 1.9v CMOS PLL for UltraSPARC Microprocessor
H-T. Ahn, Sun Microsystems, Inc., Palo Alto, CA
Abstract :
A PLL with a power supply voltage referenced loop filter for UltraSPARC
microprocessor clock generation has measured +/-25ps cycle-to-cycle
jitter at 1.9v and 360MHz. The operating frequency range is from 8.5MHz
to 660MHz and lowest power supply is 1.35v at 400MHz. The power supply
noise rejection of 1.3ps/50mv is achieved. The measured cycle-to-cycle
jitter for 400mVpp sinusoidal ac signal at power supply of 1.9v is
+/-37ps.
Back to Sessions List