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Session 6 - System-On-Chip: Trends and Real Life Applications
Chairman: Michele Taliercio - STMicroelectronics
Co-Chairman: Danesh Tavana - Triscend Corp.
2:00pm - Introduction
6.1 - 2:05pm
The Changing Landscape of System-on-a-Chip Design (invited)
A. Rincon, W. Lee, M. Slattery, IBM Microelectronics, Essex Junction, VT
Abstract :
The 1940s are remembered in electronic history for the invention of the
transistor, and the 1950s for the invention of the integrated circuit.
As the millennium comes to a close, another major development in the
world of electronic design has come to the forefront: the ability to
integrate an entire "system" onto a single computer chip.
System-on-a-chip (SOC) designs have been in existence for only a few
years; however, in that span of time, the definition of the "system"
designed and manufactured on a chip has significantly changed and
expanded as did the technology, skills, tools and methodologies required
to produce it.
This paper examines the changing
characteristics of SOC design, from the mid 1990s when there was a
limited number of processor-based in-house designs, to the present-day
definition which includes multiple processors, peripherals,
communication subsystems, bus hierarchies, analog components, and radio
frequency (RF). The increasing levels of SOC integration will be
illustrated by a family of set-top box designs.
6.2 - 2:55pm
Intellectual Property Re-use and System Emulation the Keys to succeed
the SOC Challenge: A Digital TV Application
G. Bollano, S. Claretto, L. Licciardi, A. Montanaro, L. Pilati, M.
Turolla, CSELT, Torino, Italy
Abstract :
In the ICT (Information and Communication Technologies) scenario service
evaluation, standard stabilization and the concurrent development of
hardware and software are key elements to design innovative systems.
Emulation, fast prototyping and IP re-use can really help to obtain
time-to market solutions. The papers deals with an industrial MPEG/ATM
remultiplexing equipment (REMUX) for digital TV applications in the SDVB
Switched Digital Video Broadcast) area for either satellite or cable
distribution. The paper reports the REMUX development cycle
highlighting its fast evolution from the prototype based on an embedded
system to the System on Chip realization (0.25um, ST Microelectronics
CMOS technology), mainly focusing on the effective design methodology
based on the use of Intellectual Property libraries and system
emulation.
6.3 - 3:20pm
A Single-Chip MPEG2 422@ML Video, Audio, and System Encoder with a
162-MHz Media-Processor and Dual Motion Estimation Cores
S.Kumaki, T.Matsumura, K.Ishihara, H.Segawa, K. Kawamoto, H.Ohira,
T.Shimada, H.Sato, T. Hattori, T.Wada, H.Honma, T.Watanabe, H.Sato,
K-I.Asano, T.Yoshida, Mitsubishi Electric Corporation, Hyogo, Japan,
Kanagawa, Japan
Abstract :
A single chip MPEG2 video, audio, and system encoder has been described.
It performs real-time 422@ML video encoding, Dolby Digital (AC-3)/MPEG1
audio encoding, and system stream encoding. The encoder LSI employs an
advanced hybrid architecture with a 162-MHz media-processor and
dedicated video processing hardware. Dual motion estimation cores, fine
ME for high search precision and coarse ME for a wide search range, are
integrated for optimal motion vector search. The encoder LSI is
implemented using 0.25 micron four-metal CMOS technology and integrates
11 million transistors in an area of 14.2 x 14.2 mm2.
6.4 - 3:45pm
An Analog Record, Playback and Processing System on a Chip for Mobile
Communications Devices
G. Jackson, S. Awsare, L. Engh, P. Holzmann, O. Kao, C. Palmer, A.
Raina, Information Storage Devices Inc., San Jose, CA
Abstract :
A system on chip for conditioning of voiceband analog audio signals and
non-volatile storage for use in mobile communication devices is
presented. The system allows for direct interface to acoustic transducer
elements and provides signal conditioning to gain adjust, multiplex,
filter and mix two independent signals. The system can record these
processed signals as analog samples in a non-volatile flash EEPROM array
for later retrieval. Together with the integrated signal path the system
can store up to 8 minutes of audio signal. Control of the system is
achieved via a serial interface, which is used to configure and control
the device. All necessary components of the system are provided on chip
including analog processing elements, non-volatile storage and high
voltage and reference generation.
6.5 - 4:10pm
Single GSM Mixed Signal Superchip with 96K Bytes FLASH and Low Power
Micro-Controller
K. Lee, B. Ng, A. Wang, R. Kuhn, D. Johnson, R. Kohler, Bell
Laboratories, Lucent Technologies, Allentown, PA
Abstract :
We developed a single mixed signal baseband chip performing all the
necessary signal processing required for cellular phone communication in
Global Systems for Mobile Communication (GSM) terminals. This chip is a
total GSM baseband solution consisting of voice codec, data converters,
100MHz DSP, low power micro-controller, and ASIC. The device contains a
48k-word (16 bit) programmable instruction FLASH, an 8k-word Dual-Port
Random Access Memory (DPRAM) for the data and instruction cache, and
4k-Bytes SRAM for the micro-controller. The chip size is 10.6x10.0mm2
including approximately 2.6M transistors and about 5000 analog
components implemented in 0.35um 3V linear FLASH CMOS technology.
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Session 7 - Data Converters
Chairman: Tim Rueger - Crystal Semiconductor
Co-Chairman: Doug Garrity - Motorola
2:00pm - Introduction
7.1 - 2:05pm
CMOS Pipelined ADC Employing Dither to Improve Linearity
H. Fetterman, D. Martin, D. Rich, Bell Laboratories, Lucent
Technologies, Allentown, PA
Abstract :
This paper presents a new method for applying linearity improving dither
to a pipelined A/D converter employing digital error correction. This
dither energy remains internal to the converter, only causing
correctable errors in the internal uncorrected digital data stream.
Unlike adding dither to the input signal, this new dither method does
not consume signal bandwidth or dynamic range. Spurious Free Dynamic
Range improvements of 15dB have been realized.
7.2 - 2:30pm
A 55-mW, 10-bit, 40Msample/s Nyquist Rate CMOS ADC
I. Mehr, L. Singer, Analog Devices, Inc., Wilmington, MA
Abstract :
A low power 10-bit converter which can sample frequencies above 100MHz
is presented. The converter consumes 55mW when sampling at fs=40MHz from
a 3V supply which also includes a bandgap and a reference circuit. It
exhibits higher than 9.5 effective number of bits (ENOB) for an input
frequency at Nyquist (fin=fs/2=20MHz). The differential (DNL) and
integral (INL) nonlinearity of the converter are within +/-0.3LSB and
+/-0.75LSB respectively when sampling at 40MHz, and improve to a 12-bit
accuracy level for lower sampling rates. The overall performance is
achieved using a pipeline architecture without a dedicated sample/hold
circuit at the input.
7.3 - 2:55pm
An 8-Bit 150-MHz CMOS A/D Converter
Y-T. Wang, B. Razavi, University of California, Los Angeles, CA
Abstract :
An 8-bit, 5-stage pipelined ADC employs sliding interpolation,
reinterpolation, and interleaving with clock edge reassignment.
Fabricated in a 0.6um CMOS technology, the ADC achieves a DNL of 0.62
LSB, INL of 1.24 LSB, and SNDR of 43.7dB at 150MHz sampling rate. The
converter draws 395mW from a 3.3V supply and occupies an area of 1.2x1.5
mm2.
7.4 - 3:20pm
A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak
SINAD
E. Fogleman, I. Galton, W. Huff, H. Jensen, University of California,
San Diego, CA
Abstract :
This paper presents a second-order delta-sigma modulator for audio-band
A/D conversion implemented in a 3.3V, 0.5um, single-poly CMOS process
that achieves 98dB peak SINAD and over 100dB SFDR. The design uses a
reduced-complexity, mismatch-shaping 33-level DAC and a 33-level flash
ADC with digital common-mode rejection and dynamic element matching of
comparator offsets. These signal processing innovations, combined with
established circuit techniques, enable state of the art performance in
CMOS optimized for digital circuits. To the knowledge of the authors,
this level of performance has not been achieved previously under these
process constraints.
7.5 - 3:45pm
A Spurious-Free Delta-Sigma DAC using Rotated Data Weighted Averaging
R. Radke, LSI Logic, Fort Collins, CO, A. Eshraghi, T. Fiez, Washington
State University, Pullman, WA
Abstract :
A new dynamic element matching (DEM) algorithm, referred to as rotated
data weighted averaging (RDWA), is implemented in a third-order
three-bit delta-sigma DAC with 64 times oversampling and a conversion
bandwidth of 25kHz. The systematic and random errors are considered in
the design of the 14-bit linear converter. The 2um CMOS prototype was
designed to test the performance of the DAC without DEM, with data
weighted averaging (DWA), and with RDWA. The results show that the new
RDWA algorithm is capable of achieving first-order noise shaping while
eliminating the signal-dependent harmonic distortion even for DAC
component mismatches as large as 15%.
7.6 - 4:10pm
A Bandpass Sigma-Delta Modulator IC with Digital Branch-Mismatch
Correction
V. Comino, Lucent Technologies, Holmdel, NJ, A. Lu, Hewlett-Packard
Laboratories, Palo Alto, CA
Abstract :
A bandpass sigma delta modulator, integrated in a 0.35 um CMOS
technology, samples a 82 MHz signal at 109 Ms/s. A novel digital
correction technique reduces the mismatch between the parallel branches
and makes possible a resolution of 11 bits. The technique also applies
to structures with higher levels of parallelism.
7.7 - 4:35pm
A 2.7V 11.8 mW Baseband ADC with 72 dB Dynamic Range for GSM
Applications
A. Nagari, A. Mecchia, E. Viani, S. Pernici, P. Confalonieri, G.
Nicollini, STMicroelectronics, Milan, Italy
Abstract :
This paper describes a receive baseband ADC for a GSM cellular radio
system. The circuit consists of two second-order double-sampled
semi-bilinear SD modulators followed by two 576-tap digital FIR
GSM-channel filters with offset calibration. The complete A/D achieves a
dynamic range of 72 dB and dissipates 11.8 mW from a 2.7 V supply. The
area is 1.6 mm2 in a 0.5um N-well double-poly, triple-metal CMOS
process.
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Session 8 - IC Test and Reliability
Chairman: Linda Milor - Advanced Micro Devices
Co-Chairman: Fadi Maamari - LogicVision
2:00pm - Introduction
8.1 - 2:05pm
A Low-Triggering Circuitry for Dual-Direction ESD Protection
A. Wang, Illinois Institute of Technology, Chicago, IL, C. Tsay,
National Semiconductor Corporation, Santa Clara, CA
Abstract :
A novel low-triggering, dual-direction on-chip Electrostatic Discharge
(ESD) protection circuitry is designed to protect ICıs against ESD
surges in two opposite directions. The compact circuit features low
triggering (7.5V), short response time (<1nS), symmetric deep snapback
I-V characteristics, and low on-resistance. It passed 14KV HBM ESD test
and is very area efficient (80V/um). The design was predicted by
simulation that fits measurement.
8.2 - 2:30pm
New Experimental Methodology to Extract Compact Layout Rules for Latchup
Prevention in Bulk CMOS ICs
M-D. Ker, Industrial Technology Research Institute, Hsinchu, Taiwan,
W-Y. Lo, C-Y. Wu, National Chiao-Tung University, Hsinchu, Taiwan
Abstract :
An experimental methodology has been demonstrated to find the compact
layout rules for latchup prevention in the bulk CMOS ICıs. The I/O cells
with a single guard ring and a shorter distance to the internal circuits
still have an enough latchup immunity for safe applications. The
extracted compact latchup layout rules in the 0.5-um bulk CMOS process
have been practically applied in some consumer IC products to save the
chip size but still to maintain a high latchup immunity.
8.3 - 2:55pm
Test Chips for Die Stress Characterization using Arrays of CMOS Sensors
A. Bradley, R. Jaeger, J. Suhling, Y. Zou, Auburn University, Auburn
University, AL
Abstract :
This paper demonstrates the use of special test chips containing arrays
of CMOS FET differential pairs as mechanical stress sensors and reports
the first results of measurements of packaging induced die stresses for
temperatures ranging from the epoxy cure temperature (430K) to near
liquid nitrogen temperature (90K). The experimental test chip consists
of 49 CMOS stress sensor rosettes distributed across the die and
interconnected by a novel scheme.
8.4 - 3:20pm
Digital Detection of Parametric Faults in Data Converters
B. Vinnakota, R. Harjani, University of Minnesota, Minneapolis, MN
Abstract :
Multiple parametric faults due to normal process variations are
extremely important for analog circuits. Very few analog DFT techniques
target multiple parametric faults. In this paper we present a DFT
scheme that targets high performance analog circuits. In particular, we
target a popular switched-capacitor based A/D converter. The DFT scheme
is based on an analog-to-digital capacitor ratio converter circuit. The
circuit is used to completely characterize the transfer function of a
charge redistribution A/D converter. Extensive simulation results that
include practical process variations are used to verify our DFT scheme.
8.5 - 3:45pm
Testing Analog Circuits by Supply Voltage Variation and Supply Current
Monitoring
Y. Kilic, M. Zwolinski, University of Southampton, Southampton, United
Kingdom
Abstract :
A technique for sensitizing faults in analog circuits by varying the
supply voltage and monitoring the supply current is discussed. The
detection of short circuit faults is demonstrated with a simple CMOS
circuit. The technique is applied to a larger analog circuit and
significantly improved fault cover is obtained.
8.6 - 4:10pm
TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and
Hierarchical Test Generation
Y. Makris, J. Collins, A. Orailoglu, University of California, San
Diego, CA, P. Vishakantaiah, Intel Corporation, Hillsboro, OR
Abstract :
We discuss TRANSPARENT, a hierarchical RTL testability analysis, DFT
guidance and test generation system, based transparency channels and
reachability paths, suitable for local to global test translation. Lack
of transparency pinpoints testability bottlenecks apt for DFT
modifications resulting in significant test generation efficiency
improvement, as compared to complete design ATPG.
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Session 9 - Programmable Logic Architectures
Chairman: Joe Ting - Etron Technology
Co-Chairman: Mossaddeq Mahmood - Synplicity
2:00pm - Introduction
9.1 - 2:05pm
Simplifying In-System Programming: Evolving Standards for ISP (invited)
B. Moyer, Altera Corporation, San Jose, CA
Abstract :
Traditional single-chip programming techniques for Programmable Logic
Devices (PLDs) have rapidly been replaced by the In-System Programming
(ISP) of chains of devices. Handling chains consisting of devices from
multiple chip vendors can be a significant challenge, whether for the
designer debugging a board or for production managers. The introduction
of standards into the ISP arena will make possible the practical
development of automation tools in all areas of ISP.
9.2 - 2:55pm
Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect
V. Betz, J. Rose, University of Toronto, Toronto, Ont., Canada
Abstract :
This paper examines the electrical design of FPGA interconnect
circuitry. We explore the circuit design of pass transistor and
tri-state buffer routing switches, determine which transistor sizing,
metal width and metal spacing are best for FPGA interconnect, and show
that FPGA interconnect should be electrically heterogeneous -- some
(~20%) of the routing tracks should be designed for maximum speed while
the remainder should be more area-efficient.
9.3 - 3:20pm
A Next Generation Architecture Optimized for High Density System Level
Integration
R. Cliff, S. Reddy, C. McClintock, D. Jefferson, C. Lane, K. Zaveri, M.
Mejia, A. Lee, N. Ngo, R. Altaf, B. Pedersen, F. Heile, J. Schleicher,
J. Turner, Altera Corporation, San Jose, CA
Abstract :
We have developed a next generation architecture called APEX(TM) to
improve overall logic efficiency, performance and provide a framework to
add a much broader range of features which enables complete system level
integration of a users system. This new architecture will support a
family of devices exceeding 2 million gates in density. Density and
speed improvements are achieved through an enhanced hierarchical routing
structure.
9.4 - 3:45pm
A Fast, Predictable FPGA with PLLs, Dual Port SRAMs and Active Repeaters
P. Sasaki, Y. Bobra, W. Cory, A. Ghia, S. Menon, M. Kola, M. Thomas, P.
Rau, A. Zaliznyak, DynaChip Corporation, Sunnyvale, CA
Abstract :
A new FPGA architecture is presented that provides predictable high
performance coupled with special features. Patented active repeater
technology provides predictable high performance. Standard features are
enhanced by the inclusion of analog PLLs, dual port SRAMs and the
ability to interface to multiple I/O interface standards.
9.5 - 4:10pm
A Field Programmable System Chip which Combines FPGA and ASIC Circuitry
W. Andrew, G. Carl, R. Charath, J. Hoff, R. Modo, H. Nguyen, W. Smith,
D. Rhein, J. Schulingkamp, C. Spivak, J. Steward, A. Subramaniam, Lucent
Technologies, Allentown, PA
Abstract :
The industry's first combination of FPGA and ASIC technologies is
discussed in this paper. This chip known as Field Programmable System
Chip (FPSC), combines a regular array of SRAM based FPGA programmable
function units (PFUs) and an ASIC area in which any ASIC application
which fits the usable area can be implemented. An interface block allows
the transfer of data and clocks between the two circuit types. An
additional feature is the ability to "program" the ASIC area using RAM
bits in the FPGA bit stream that are set aside for this purpose
providing the user added flexibility. This paper will describe the
OR3TP12, an FPGA device with embedded 66 MHz/64 bits PCI core. A circuit
allowing the user to program the FPGA through the PCI interface will
also be discussed.
9.6 - 4:35pm
A 4.9ns, 3.3 Volt, 512 Macrocell, CMOS PLD with Hot Socket Protection and
Fast In System Programming
B. Vest, G. Liang, M. Chan, E. Chun, M. Fiester, W. Ding, E. Lau, G.
Lin, B. Nouban, D. Reese, M. Smith, N. Tran, S. Wong, M. Woo, M. Wong,
J. Costello, Altera Corporation, San Jose, CA
Abstract :
A high density, Programmable Logic Device (PLD) family developed for hot
socketing and high performance is discussed. The family is fabricated on
a 0.32um quadruple layer metal process. The largest family member is a
512 macrocell part with typical pin to pin delays of 4.9ns. The design
techniques and testing methodology to guarantee safe hot socketing are
described. Streamlined In System Programming (ISP) and circuits used to
configure EEPROM cells with a 3.3-V supply are also discussed.
9.7 - 5:00pm
Flexible Reconfigurable Multiplier Blocks Suitable for Enhancing the
Architecture of FPGAs
S. Haynes, A. Ferrari*, P. Cheung, Imperial College, London, England,
*University de Aveiro, Aveiro, Portugal
Abstract :
A new architecture is proposed for configurable blocks which can be used
to dynamically construct multipliers. An array of these blocks are
capable of being configured to perform any 8m by 8n bits signed/unsigned
binary multiplication. The new design is based on the radix-4 overlapped
multiple-bit scanning algorithm. This yields excellent multiplication
times, at the same time allowing multiply accumulate (MAC) operations,
without modification. The new design is compared to our previous scheme,
and shown to be both faster and require fewer transistors.
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