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Session 2 - Advanced RF Circuit Simulation and Modeling
Chairman: Peter Feldmann - Lucent Technologies, Bell Labs
Co-Chairman: Stephen Rochel - Simplex Solutions
10:00am - Introduction
2.1 - 10:05am
Simulation and Modeling of Intermodulation Distortion in Communication
Circuits
J. Chen, D. Feng, J. Phillips, K. Kundert, Cadence Design Systems, San
Jose, CA
Abstract :
Recent improvements to the mixed frequency/time algorithm expand our
ability to predict distortion along the signal path of RF transceivers.
The MFT algorithm can compute the intermodulation distortion of large
circuits driven by discrete tones or can be used to construct a
macromodel that rapidly predicts spectral regrowth in transmitters
processing complex digitally modulated signals.
2.2 - 10:30am
Intermodulation Analysis of Mixer Circuits Based on Frequency Domain
Relaxation Method
A. Ushida*, Y. Yamagami*, Y. Nishio*, M. Takahashi**, K. Ogawa**,
*Tokushima University, Tokushima, Japan, **Sony Corporation, Kanagawa,
Japan
Abstract :
There are many communication circuits driven by multi-tone signals such
as modulators and mixers. If the output frequency components are largely
different in each other, the brute force numerical method will take an
enormous computation time to calculate the steady-state responses,
because the total period becomes very long. In this paper, we show a
SPICE oriented algorithm based on the frequency domain relaxation method
which can be efficiently applied to relatively large scale ICs.
2.3 - 10:55am
Grid Selection Strategies for Time-Mapped Harmonic Balance Simulation of
Circuits with Rapid Transitions
O. Nastov, Motorola, Inc., Austin, TX, J. White, Massachusetts Institute
of Technology, Cambridge, MA
Abstract :
The Time-Mapped Harmonic Balance (TMHB) method overcomes the
inefficiency of standard Harmonic Balance for computing steady-state
solutions of circuits with rapid transitions. TMHB features a
non-uniform grid to resolve the sharp features in the signals. The
success of TMHB is critically dependent on the selection of this
non-uniform grid. After a brief discussion of TMHB, two grid selection
strategies, direct and iterative, are examined. Results on several
circuit examples indicate that the iterative strategy is the best.
Compared to standard Harmonic Balance, up to five orders of magnitude
accuracy improvements, and up to a factor of six simulation time
speedups and memory savings are achieved.
2.4 - 11:20am
Automated Macromodelling of "Nonlinear" Wireless Blocks
J. Roychowdhury, Bell Laboratories, Murray Hill, NJ
Abstract :
Behavioral modelling of blocks is an important step in wireless system
verification. In this paper, we describe the application of an
automated technique for macromodel extraction. Called TVP, the
technique works directly from detailed transistor-level descriptions
(e.g., SPICE) of a block to produce system-level macromodels (e.g.,
suitable for MATLAB). A key property of TVP is that it can reduce blocks
with switching, sampling or frequency-translation properties. TVP is
efficient for large circuits and can tailor the size of the macromodel
to meet a specified accuracy. TVP also produces dominant poles and
zeros without need for lengthy simulations. We present applications to
RF mixers and switched-capacitor filters, to obtain size reductions of
more than two orders of magnitude with no appreciable loss of accuracy.
2.5 - 11:45am
A Frequency-Domain, Volterra Series-Based Behavioral Simulation Tool for
RF Systems
I. Vassiliou, A. Sangiovanni-Vincentelli, University of California,
Berkeley, CA
Abstract :
In this paper a new behavioral modeling approach for RF systems is
presented, based on a Volterra series input-output map representation.
The modeling is done purely in the frequency domain, capturing the
typical system-level specifications for RF building blocks, independent
of the implementation details. A harmonic balance simulation tool has
been developed based on those models. The implementation focuses on
deterministic effects such as distortion and frequency conversion. The
behavioral simulator has been tested for various systems and results are
presented.
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Session 3 - IP Creation and Protection
Chairman: Michael Berry - Silicon Logic Engineering
Co-Chairman: Thomas Zimmermann - Motorola GmbH
10:00am - Introduction
3.1 - 10:05am
A Fully Synthesizable Parameterized Viterbi Decoder
R. Burger, G. Cesana, STMicroelectronics, Agrate, Italy, M. Paolini, M.
Turolla, S. Vercelli, CSELT, Torino, Italy
Abstract :
The Viterbi Algorithm is widely used in digital communications. It
realizes the maximum-likelyhood decoding of convolutional codes received
from a noisy channel. Depending on the application (terrestrial,
satellitar, digital modems, digital cellular telephone applications and
others) a Viterbi Decoder must be designed to respect specific
requirements such as small area, high speed or maximum efficiency. This
paper presents a parameterized implementation of this algorithm for
design reuse purposes, in order to allow the implementation of the most
optimized solution for each application, exploiting input parallelism,
sharing the ACS units, adjusting depth of computation and BER
computation.
3.2 - 10:30am
Fast and Accurate Power Verification of a Viterbi Decoder IP based on
Mixed-Level Power Simulation Technique with Automatic Spatio-Temporal
Circuit Partitioning
M. Chinosi, R. Zafalon, C. Guardiani, STMicroelectronics, Agrate
Brianza, Italy
Abstract :
A new technique for spatial and temporal partitioning of a logic circuit
simulation, based on the nodes activity computed at an higher level of
abstraction is presented. The methodology is suitable for parallel
implementation on a multi-processor environment and allows switching
between fast and detailed level of abstraction during the simulation
run. This technique applied to a IP Viterbi Decoder has performed a
considerable reduction in CPU time and memory allocation yet keeping the
accuracy of the electric simulation.
3.3 - 10:55am
Watermarking-Based Copyright Protection of Sequential Functions
I. Torunoglu, E. Charbon, Cadence Design Systems, Inc. San Jose, CA
Abstract :
Watermarking is proposed as a mean to protect intellectual property
contents of electronic systems from copyright infringement. The paper
focuses on regular sequential functions operating on finite input/output
sets. This is an important class of circuits, as it is the basis of most
digital controllers. The technique consists of implanting indelible
stamps in the circuit's inner structure, while not disrupting its
functionality or degrading its performance. Algorithms are proposed for
implanting and detecting watermarks so as to minimize implementation
overhead for a required robustness.
3.4 - 11:20am
Hierarchical Watermarking for Protection of DSP Filter Cores
A. Rashid, J. Asher, W. Mangione-Smith, M. Potkonjak, University of
California, Los Angeles, CA
Abstract :
A hierarchical watermarking approach is developed that incorporates an
ownership identification directly into the design development process.
This approach offers a high degree of tamper resistance and provides
easy, non-invasive copy detection. We present two FIR digital filter
cores, one watermarked at the algorithm level and the second at the
algorithm and architecture levels. A unique ownership signature
(watermark) is placed at each level. At the algorithm level, the
watermark is embedded in the filter coefficients during the development
of the transfer function. At the architecture level, we use circuit
transformations to watermark the design. Experimental results show
approximately 7% area overhead of the algorithm-level watermarked design
over a non-watermarked design. The cost of area for the design
watermarked at both the algorithm and architecture levels is less than
40%.
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Session 4 - IC Design Project Management
Chairman: John Wright - American Microsystems Inc.
Co-Chairman: Henry Chang - Cadence Design
10:00am - Introduction
4.1 - 10:05am
Multi-Project Management in Real Time
K. Au, Motorola Inc., Austin, TX, T. Mann, Advanced Management Solutions
Inc., Redlands, CA
Abstract :
Investment return is related to the IC development life cycle.
Decision check points are identified throughout the development
cycle. Project management responsibility and skill set are discussed.
Two concurrent projects with resource overlap illustrate the
implementation of a project management process. An interactive
management tool was used to demonstrate results.
4.2 - 10:55am
Integrated IC Design Approach based on Software Engineering Paradigm
S. Sinha, M. Mehendale, Texas Instruments (India), Ltd., Bangalore,
India
Abstract :
The paper presents an approach for managing large, multi-site IC design
project. The approach is based on software engineering paradigm. The
paper highlights the overlap between the domains of software and IC
design and shows how it can be used to leverage well-used, matured
techniques from software engineering domain. This methodology has been
successfully employed for the processor design of TMS320C27XX DSP.
4.3 - 11:20am
Beyond 1 GHz
H. Hofstee, K. Nowka, IBM Austin Research Laboratory, Austin, TX
Abstract :
This presentation reports on ongoing work at the IBM Austin Research
Laboratory following the development of the 1GHz microprocessor
prototype. We discuss how to realize larger microprocessor designs
without sacrificing cycle time, and we discuss some of the challenges we
face in achieving frequencies that are significantly higher than 1GHz.
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Session 5 - Audio and Video Signal Processing
Chairman: Grady Cook - Texas Instruments
Co-Chairman: Neil Weste - Macquarie University
10:00am - Introduction
5.1 - 10:05am
A Scalable Architecture for MPEG-4 Embedded Zero Tree Coding
B. Vanhoof, M. Peon, G. Lafruit, J. Bormans, M. Engels, I. Bolsens,
IMEC/DESICS, Heverlee, Belgium
Abstract :
Within MPEG-4, textures for 3D rendering are compressed using wavelets.
The OZONE implements a dedicated, scalable hardware architecture for
embedded zero tree coding, the crucial part in the wavelet compression
scheme. With an operating frequency of 32 MHz, visual lossless
compression of over 30 CIF images per second is achieved.
5.2 - 10:30am
A MPEG4 Programmable Codec DSP with an Embedded Pre/Post-Processing
Engine
S. Kuromaru, M. Matsuo, H.Nakajima, Y.Kohashi, T. Yonezawa, T. Moriiwa,
M. Ohashi, M.Toujima, T.Nakamura, M. Hamada, T.Hashimoto, H.Fujimoto,
Y.Iizuka, J. Michiyama, H. Komori, Matsushita Electric Industrial Co.
Ltd., Fukuoka, Japan
Abstract :
We have developed a programmable DSP with embedded video
pre/post-processing engine for MPEG4, H.263 and wavelet-based
algorithms. This chip can perform high performance video codec with
processing capability of CIF format at 15frame/sec, or video/speech
codec with processing capability of QCIF format at 30frame/sec and
G.723.1, according to target systems.
5.3 - 10:55am
A Low-Power Single-Chip MPEG-2 CODEC LSI
Y. Tsuboi, H. Arai, M. Takahashi, M. Oku, Hitachi, Ltd., Yokohama, Japan
Abstract :
A single-chip MPEG-2 CODEC LSI design has been completed. The CODEC
functions, i.e. both encoding and decoding functions, are provided.
This LSI is being fabricated in a 0.18um CMOS 5-layer metal technology.
Small chip size and low power consumption less than 500 mW are expected.
This LSI is fully synthesizable from RTL source codes written in
Verilog-HDL and easily adaptable to various IP (Intellectual Property)
blocks.
5.4 - 11:20am
Embedding DRAM in Single chip MPEG1 CODEC LSI
T. Fujihira, H. Ohtsubo, Hitachi Ltd., H. Sakurai, K. Ohi, Hitachi Video
& Information Systems Ltd., Yokohama, Japan
Abstract :
We have successfully designed the low power single chip MPEG1 CODEC LSI
which is the most suitable for portable devices such as digital camera.
By adopting compact and efficient motion estimation process and
embedding SDRAM for storing image data inside, this chip realizes
compactness and low power of the system.
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