CICC 1999 Ed Sessions: E-3 - Advanced Integration Issues

Moderator: David Rich, Lucent Technologies, Bell Labs
Assistant: Phil Diodato, Lucent Technologies, Bell Labs

E3.1: Process Integration of Embedded DRAM

Hidemi Ishiuchi, Toshiba

8:00am - 9:50am

This talk will provide the LSI designer with an introduction to process integration of embedded DRAM. After brief overview of the embedded DRAM technology, tradeoffs in the DRAM cell selection will be discussed. The process integration scheme of the embedded DRAM is not unique; there can be wide variety of process options. The key issues in the process integration will be presented including gate oxide thickness, work function of the gate of MOSFETs, drain engineering, salicide technology, well structure, local interconnects, multilevel metal interconnects, etc. Trends in the embedded DRAM technologies will also be presented.

E3.2: SPICE Modeling: The Good, The Bad, and the Ugly

Colin McAndrew, Motorola

10:10am - 12:00pm

This course details capabilities, limitations, and problems with SPICE models and parameter extraction. Topics include: physical process and geometry dependence as the rational basis for models; the subtle but critical difference between model parameters and measured parameters; characterization criteria that address design needs, not generic numerical goals; simple efficient, and accurate statistical modeling; the principle of asymptotic correctness; loop closure (efficient verification that design models accurately represent manufacturing). In addition, common and fundamental modeling problems will be exposed: how to detect them; why they exist; what are their ramifications for design; why delta-W isn¹t and why Ohm¹s law isn¹t.

E3.3: Advanced Embedded Memory Technologies and Design Issues

Kenji Noda, NEC

1:00pm - 2:50pm

This lecture provides an overview of advanced embedded memory technologies and design issues on the integration. After reviewing the difference between commodity DRAM and CMOS logic devices, advanced merged-DRAM/ASIC approaches will be discussed. The other key topic in this talk is a comparison of 1T/1C-DRAM, 6T-SRAM and Loadless-4T-SRAM, which has been proposed at IEDM '98, in terms of performance and fabrication cost.

E3.4: Building-In Reliability

Timothy Rost and William Hunter, Texas Instruments

3:10pm - 5:00pm

As increasing investments are made in VLSI technology and development, it becomes essential that designs have reliability issues addressed prior to volume manufacturing. Ideally, reliability issues would be addressed and corrected during the design process. This tutorial provides a basic review of reliability wear-out mechanisms, a discussion of how reliability mechanisms can be checked and corrected in the design phase, and how emerging process technologies such as Cu interconnects and low-K dielectrics will influence reliability design guidelines.