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Technical
Program
Educational Sessions
Keynote Address
Conference Luncheon
Panel Discussions
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New This Year
Sunday Afternoon Presentation Skills Session
Cost of this special session is $50.00. This session is NOT included in the Educational Session Fee
Effective Technical Writing and Presentations
Silicon Valley Room, Sunday Afternoon, September 21
2:00 pm - 5:00 pm
Effective Technical Writing and Presentations
Ann Marie Rincon (ON Semiconductor)
My technical work is outstanding - why didn't my paper get accepted? I thought my description was very clear - why was my thesis misunderstood?
This class will provide answers to these questions and help engineers and programmers write clear, concise technical papers. The writing do's and don'ts covered in this class can
be applied to other technical documents such as application notes, product specifications and emails.
The class will provide:
A standard technical paper outline and a description of each section
Tips for submitting a paper to an external conference
General writing tips including do's and don'ts
Tips for translating your technical paper into an effective presentation
Several lucky attendees will receive a copy of "The Elements of Style" by William Strunk Jr. and E.B. White.
Following is the 2008 Educational Session Program
EDUCATIONAL SESSIONS
Sunday, September 21
Chairperson: Shahriar Mirabassi, University of British Columbia
Educational Session 1
High-Speed I/O
Oak Ballroom, Sunday, September 21
Organizer: Tony Chan Carusone, University of Toronoto
Co-Organizer: George LaRue, Washington State University
9:00 am - 10:50 am
E1-1 Multi-Gigabit I/O Design for Microprocessor Platforms
Randy Mooney (Intel)
A discussion of the constraints of the design space for microprocessor platforms, and a look at the state of the technologies required to deliver bandwidth in these platforms.
These technologies include analysis tools, interconnect components, modulation and equalization choices that fit the constraints, and the various circuits required in silicon. This is followed
by a look at future platform requirements, and the potential solution space to meet those needs.
11:10 am - 1:00 pm
E1-2 Jitter and Signal Integrity at 10 Gbps
Mike Li (Altera Corp.)
In this tutorial presentation, we will first review where the technology is heading to for the multiple Gbps high-speed links and I/O buses for devices and systems in networks and computers.
Second, we will discuss why jitter and signal integrity have become the major challenges, as well as limiting factors for developing those high-speed, high performance, high volume, and low-cost I/O
devices and systems as the data rate approaches 10 Gbps and beyond. Third, we will discuss the jitter and signal integrity modeling, simulation, verification and characterization methodologies within the
context of a serial link. We will cover these ever evolving cutting edge topics from generic perspective, as well as practical application perspective, with real-world examples from multiple Gbps link
technologies such as Giga Bit Ethernet (GBE), PCI Express (PCIe), Fibre Channel (FC), with emphasizes on their latest generations operating at single lane data rates in the vicinity of 10 Gbps. Emerging
challenges such as jitter amplification and mitigation, equalization optimization and verification, on-chip jitter de-embedding will also be covered.
2:00 pm - 3:50 pm
E1-3 Equalization & High-Speed Transceiver Design
Jared Zerbe (Rambus)
Equalization is an ever-critical aspect of serial data systems and is even beginning to expand into high-speed parallel systems. This tutorial provides a basic overview of the serial data transmission
problem and the goals of equalization, along with some of the practical challenges at high speeds and some vision of its future. The architecture of equalized systems is explained, with detail on key types
of equalizers such as linear receive equalizers, transmitter pre-emphasis, and DFE, along with the pros and cons of each type. The tutorial will also teach how various equalizer components can be used
together to mitigate each other's weaknesses. Equalizers will be presented from various viewpoints, including effectiveness and practical circuit design as well as future trends, and effectiveness of
different approaches on different practical environments will be compared. Simulation approaches for equalization will be discussed. Finally, as an alternate to equalization, certain modulation approaches
such as 4-PAM & duo-binary will be covered and pros and cons reviewed.
4:10 pm - 6:00 pm
E1-4 Clocking and CDRs
Jafar Savoj (Qualcomm)
High-purity clock generation enables longer reach in wired communication systems. Optical and copper standards set an upper bound on the maximum noise and distortion added to the signal at the
source. This tutorial describes means of efficient clock generation and distribution in high-performance chips to satisfy requirements imposed by the standards. Clock and data recovery (CDR) circuits are
an integral part of wired communication systems. With the accelerated rate of device scaling in recent decades, CDR architectures have transitioned from fully analog into mixed-mode and digital
implementations. The tutorial later addresses the evolution of CDR architectures, as well as the design of their building blocks.
Educational Session 2
Coping with Technology Scaling
Fir Ballroom, Sunday, September 21
Organizer: Colin McAndrew, Freescale Semiconductor
9:00 am – 10:50 am
E2-1 Technology and Reliability
Paul Packan (Intel)
Continued technology scaling drives not only developments and changes in device designs, characteristics, and performance, but also involves an ever expanding complexity of
constraints that must be applied and phenomena, like variability and stress, that must be taken into account to enable the design of billion+ transistor ICs. This tutorial will review nMOS
and pMOS scaling trends and their impact on circuit performance benchmarks, including power. Sources of variability and their impact on circuit performance at scaled supply voltages will be reviewed,
as will circuit level techniques to mitigate problems caused by variability. The impact of both device and circuit architectures will be discussed, as related to memories, RF circuits, power consumption,
and performance. Scaling has also lead to issues with reliability, and these will be reviewed. Finally, because of the growing complexity of restrictions that must be applied to make functions ICs, lithography,
layout, and design rule issues that affect the manufacturability of designs will be discussed.
11:10 am – 1:00 pm
E2-2 Logic and Memory Scaling Challenges
Bora Nikolic (University of California, Berkeley)
Digital logic and memory are expected to scale down in area by 50% with each new technology node. This is the only key benefit of technology scaling as the active and leakage power limit the rate
of further logic speed increase. This tutorial will address the main challenges and known solutions for keeping the expected scaling rate: increased cost of design and manufacturing, design under power
limitation, impact of technology variability, and design with added technology features.
2:00 pm – 3:50 pm
E2-3 CAD and Modeling Issues
Sani Nassif (IBM)
Technology scaling is not just a problem for the manufacturing engineers; it presents unique challenges for those who must use this same technology to produce working high performance
chips in volumes that can lead to profit. Activities like OPC and DFM have become common place terms for designers and EDA engineers, and are all part of the response to the increasing
complexity of the design/manufacturing interface. This interface has historically been defined by layout design rules and so-called corner models. Both of these representations are unraveling as
we enter the 45nm node with thousands of design rules, and with overall manufacturing variability becoming the most significant challenge faced by design. In this tutorial, we will review the design/manufacturing
interface and show current trends, explain how technology characterization and modeling leads to specific challenges for the representation of technology in simulation tools, and finally review some of the design
responses to technology scaling that leverage adaptivity and regularity.
4:10 pm – 6:00 pm
E2-4 Analog and RF Design Issues in Deep Submicron CMOS Technology
Behzad Razavi (University of California, Los Angeles)
This tutorial presents the challenging issues in analog and RF design as technology nodes go beyond 65 nm and 45 nm. Noise-power-speed and mismatch-power-speed trade-offs resulting from supply
scaling are quantified and the effect of switch nonlinearities in sampling circuits is formulated. Phenomena such as output resistance nonlinearity and the gate leakage current are studied and their impact
on circuits such as PLLs and op amps is summarized. Noise-linearity trade-offs in passive and active RF mixers and various deep-submicron effects in LC oscillators are also presented and low-voltage circuit
techniques are described.
Educational Session 3
Fundamentals of Analog Design
Pine Ballroom, Sunday, September 22
9:00 am - 10:50 am
E3-1 Amplifiers
Boris Murmann (Stanford University)
This lecture covers a systematic methodology for the design of high performance operational transconductance amplifiers (OTAs) in deep sub-micron CMOS technology. The first part of this presentation
reviews the basic design equations and power/speed/noise tradeoffs in OTAs using a two-stage Miller-compensated design as an example. In the second part, Spice-generated look-up tables are introduced as
a means to bridge the gap between simulation, hand analysis and Matlab optimization. Using tabulated device data that captures the fundamental tradeoff between speed (gm/Cgg) and transconductance efficiency
(gm/ID), the proposed method yields near-optimal designs without the need for iterative Spice simulations or expensive CAD tools.
11:10 am - 1:00 pm
E3-2 References
Wing-Hung Ki (Hong Kong University of Science and Technology)
In this lecture, the treatment of voltage references that is systematic and coherent, rigorous but not excessive is attempted. The talk starts with fundamentals of voltage references.
Popular bandgap references (BGRs) are then discussed, with emphasis on CMOS bandgap references using parasitic BJTs in a CMOS process. Performance parameters such as temperature coefficient,
power supply rejection, line and load regulation, and loop gain are introduced. For BGR with simple structures, analytic results on loop gain and power supply rejection are presented. The development of op-amp
based BGR for reducing effect due to op-amp input offset voltage, folded resistor for lowering power supply voltage (Vdd) requirement, and folded resistor divider for further lowering Vdd requirement, are traced.
Non-op-amp based BGRs are discussed, starting with the 4T current-voltage-mirror (CVM) scheme in replacing the op-amp. The principle of symmetrical matching is then introduced to minimize systematic
errors due to channel length modulation, and an 8T symmetrically matched CVM is used to realize a BGR with improved power supply rejection. The CMOS deep n-well process, and designmBGRs discussed are
designed using a 0.18 procedure and simulation results are presented. Design issues such as trimming, resistor strings and organization of voltage references in an IC system are also sketched.
2:00 pm - 3:50 pm
E3-3 PLL
Behzad Razavi (UCLA)
This tutorial deals with the analysis and design fundamentals of PLLs. Various voltage-controlled ring oscillator topologies are described that can be used in timing applications up to several gigahertz.
Next, type I PLLs and their shortcomings are studied, leading to type II (charge-pump) PLLs as a superior choice. The dynamics of the PLLs are derived, the effect of various charge pump nonidealities is
presented, and circuit techniques for alleviating these effects are summarized. Lastly, a design procedure for PLLs is outlined and demonstrated by a transistor-level implementation.
4:10 pm - 6:00 pm
E3-4 DAC
Doug Mercer (Analog Devices)
Modern communication systems have spawned a growing interest in high performance, high speed Digital to Analog Converter designs which can be easily embedded into larger mixed signal systems.
Implementing larger systems in addition require peripheral support D/A functions outside the main signal path in applications such as tuning and calibration. The tutorial will concentrate on D/A converter design
in MOS process technologies and cover these three topics.
1) A brief look Digital to Analog conversion first principles including a description of the D/A function and the key specifications that define the performance of a D/A.
2) Common D/A architectures will be explored with these first principles in mind. The advantages and disadvantages of each will discussed.
3) Case studies of example CMOS implementations will be included.
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